Roger Ang and Nikil Dutt revised April 23, 1992 Department of Information and ...  Home/Search
Context
Related
| uci.edu/pub/cad/ca...rescheduling.ps.gz Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: uci.edu/pub/cad/cadlabtr...INDEX (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: Traditionally, high-level synthesis (HLS) has been a fully automatic process over which the user has had little or no control. To make HLS an acceptable methodology for expert designers, we need to allow for more interactivity during synthesis. Since the scheduling step in HLS often determines the scope and quality of the ensuing synthesis tasks, we describe behavior-preserving transformations for manual rescheduling of behavior. We present the Structured Finite State Machine (SFSM) design... (Update)
Active bibliography (related documents): More All
0.9: On Linking RT-Component Functionality to Abstract HDL . . . - Ang, al. (1992) (Correct)
0.6: Recent Developments in High-Level Synthesis - Lin (1997) (Correct)
0.5: Technology Mapping for Minimizing Gate and Routing Area - Aiguo Lu Guenter (Correct)
Similar documents based on text: More All
0.3: Exploiting Off-Chip Memory Access Modes in High-Level Synthesis - Panda, Dutt, Nicolau (1997) (Correct)
0.3: An Algorithm for the Allocation of Functional Units from.. - Roger Ang (1994) (Correct)
0.3: Backward-Annotation of Post-Layout Delay Information.. - Park, Kim, Chang.. (1999) (Correct)
BibTeX entry: (Update)
@techreport{ ang92transformations,
author = "Roger Ang and Nikil Dutt",
title = "Transformations Supporting Interactive Rescheduling for High-Level Synthesis",
number = "ICS-TR-92-20",
pages = "22",
year = "1992",
url = "citeseer.ist.psu.edu/394191.html" }
Citations (may not include all citations):866 Techniques and Tools (context) - Aho, Sethi et al. - 1986
217 High-Level Synthesis: Introduction to Chip and System Design (context) - Gajski, Dutt et al. - 1992
46 Retiming and Resynthesis: Optimizing Sequential Networks wit.. (context) - Malik, Sentovich et al. - 1991
44 Behavioral Transformation for Algorithmic Level IC Design - Walker, Thomas - 1989
42 Optimizing Resource Utilization using Transformations (context) - Potkonjak, Rabaey - 1991
22 Design Representation for the Synthesis of Behavioral VHDL M.. (context) - Camposano, Tabet - 1989
20 Synthesizing Circuits from Behavioral Descriptions (context) - Camposano, Rosenstiel - 1989
19 Behavior-preserving Transformations for High-Level Synthesis (context) - Camposano - 1990
16 Flow Graph Representation (context) - Orailogulu, Gajski - 1986
11 A New Synthesis Algorithm for the MIMOLA Software System (context) - Marwedel - 1986
10 The Value Trace: A Data Base for Automated Digital Design (context) - McFarland - 1978
10 Chippe: A System for Constraint Driven Behavioral Synthesis (context) - Brewer, Gajski - 1990
4 An Optimizer for Hardware Synthesis (context) - Bhasker, Lee - 1990
4 Optimizations in High Level Synthesis (context) - Rosenstiel - 1986
3 Data Flow Graphs: System Specification with the Most Unrestr.. - DeJong - 1991
3 A User Interface for VHDL Behavioral Modeling (context) - Dutt, Cho et al. - 1991
2 DAGON: Technology Binding and Logic Optimization by DAG Matc.. (context) - Keutzer - 1987
2 An Intermediate Representation for Behavioral Synthesis (context) - Dutt, Hadley et al. - 1990
1 Preserving Design Behavior without Register-Transfer Equival.. (context) - Leeser, Wolf - 1991
1 A Transformation Package for the Behavioral Level of the CMU.. (context) - Walker - 1982
1 Increasing User Interaction During High-Level Synthesis (context) - Walker, Ramabadran et al. - 1991
1 A Decision Support Environment for Behavioral Synthesis (context) - Hadley, Gajski - 1991
1 A Design Representation for High-Level Synthesis (context) - Rundensteiner, Gajski - 1990
Documents on the same site (http://www.ics.uci.edu/pub/cad/cadlab-trs/1992/INDEX.html): More
A System-Level Specification & Design Methodology - Gajski, Narayan, Vahid (1992) (Correct)
Architectural Tradeoffs in Synthesis of Pipelined Controls - Ramachandran, Gajski (1992) (Correct)
On Linking RT-Component Functionality to Abstract HDL . . . - Ang, al. (1992) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC