Amarildo T. da Costa Felipe M. G. Franca Eliseu M. C. Filho Dept. of Systems...  Home/Search
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Abstract: Dynamic Trace Memoization (DTM) is a reuse technique that employs memoization tables to skip the execution of sequences of redundant instructions. DTM thus extends the concept of instruction reuse to larger grained units and, contrary to other proposed reuse schemes, it is not constrained by architectural parameters nor code-level boundaries. For the benchmark programs in the SPECInt95 suite, evaluation results show that DTM improves performance by 5% to 21% with an average of 9.3%. For the... (Update)
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BibTeX entry: (Update)
@misc{ costa-evaluating,
author = "Amarildo Da Costa",
title = "Evaluating DTM in a Superscalar Processor Architecture",
url = "citeseer.ist.psu.edu/385638.html" }
Citations (may not include all citations):1575 Computer Architecture: A Quantitative Approach (context) - Patterson, Hennessy - 1997
230 Compiler Transformations for High-Performance Computing - Bacon, Graham et al. - 1994
146 A Comparison of Dynamic Branch Predictors that Use Two Level.. - Yeh, Patt - 1993
145 Exceeding the Dataflow Limit Via Value Prediction - Lipasti, Shen - 1996
79 Computer Science Department (context) - Burger, Austin et al.
74 Memo Functions and Machine Learning (context) - Michie - 1968
39 An Empirical Analysis of Instruction Repetition (context) - Sodani, Sohi - 1998
32 Understanding the Differences Between Value Prediction and I.. (context) - Sodani, Sohi - 1998
26 Exploiting Basic Block Value Locality with Block Reuse - Huang, Lilja - 1999
21 Trace-Level Reuse (context) - Gonzalez, Tubella et al. - 1999
12 Two Fast and High-Associativity Cache Schemes - Zhang, Zhang et al. - 1997
8 Datapath Design for a VLIW Video Signal Processor - Wolfe - 1997
7 DEC Western Research Laboratory (context) - McFarling, Predictors et al. - 1993
7 PowerPC 750 RISC Microprocessor Technical Summary (context) - Motorola - 1997
6 The Anatomy of a High-Performance Microprocessor -- A System.. (context) - Shriver, Smith - 1998
6 of the 24th International Symposium on Computer Architecture (context) - Sodani, Sohi et al. - 1997
2 ith, The Predictability of Data Values, Proc. of the 30th In.. (context) - Sazeides, Sm - 1997
2 NEUROCOM - Integrating Neurocomputing and Conventional Compu.. (context) - Rebello - 1997
1 Active Instruction Out-of-Order-Execution Processor (context) - Williams, Patkar et al. - 1995
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The Dynamic Trace Memoization Reuse Technique - Costa, Franca, Filho (2000) (Correct)
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