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A Case for Intelligent RAM (1997)  (Make Corrections)  (45 citations)
David Patterson, et al.
IEEE Micro



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Abstract: This article reviews the state of microprocessors and DRAMs today, explores some of the opportunities and challenges for IRAMs, and finally estimates performance and energy efficiency of three IRAM designs. (Update)

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Design and Optimization of Large Size and - Low Overhead Off-Chip   (Correct)
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13:   Memory bandwidth limitations of future microprocessors - Burger, Kagi et al. - 1996
10:   Missing the Memory Wall: The Case for Processor/Memory Integration (context) - Saulsbury, Pong et al. - 1996
7:   Computer Architecture: a Quantitative Approach (context) - Hennessy, Patterson - 1996

BibTeX entry:   (Update)

D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Thomas, and K. Yelick, "A case for intelligent RAM," IEEE Micro, March 1997, vol. 17, no. 2, pp. 34--43. http://citeseer.ist.psu.edu/article/patterson97case.html   More

@article{ patterson97case,
    author = "David Patterson and Thomas Anderson and Neal Cardwell and Richard Fromm and Kimberly Keeton and Christoforos Kozyrakis and Randi Thomas and Katherine Yelick",
    title = "A Case for Intelligent {RAM}",
    journal = "IEEE Micro",
    volume = "17",
    number = "2",
    month = "\slash",
    pages = "34--44",
    year = "1997",
    url = "citeseer.ist.psu.edu/article/patterson97case.html" }
Citations (may not include all citations):
110   Memory Bandwidth Limitations of Future Microprocessors - Burger, Goodman et al. - 1996  ACM   DBLP
99   Hitting the Memory Wall: Implications of the Obvious - Wulf, McKee - 1995  ACM
65   Studies of Windows NT Performance Using Dynamic Execution Tr.. - Perl, Sites - 1996  ACM   DBLP
64   Missing the Memory Wall: The Case for Processor/Memory Integ.. (context) - Saulsbury, Pong et al. - 1996  DBLP
38   The J-Machine Multicomputer: An Architectural Evaluation - Noakes, Wallach et al. - 1993  DBLP
37   The Energy Efficiency of IRAM Architectures - Fromm - 1997  ACM   DBLP
25   The M-Machine Multicomputer - Fillo - 1995  ACM   DBLP
19   Computer Organization and Design (context) - Hennessy, Patterson - 1997  ACM
18   Combined DRAM and Logic Chip for Massively Parallel Systems (context) - Kogge - 1995  ACM
15   A Multimedia 32 b RISC Microprocessor with 16 Mb DRAM (context) - Shimizu - 1996
15   Parallel Processing RAM Chip with 256Mb DRAM and Quad Proces.. (context) - Murakami, Shirakawa et al. - 1997
14   Intelligent RAM (IRAM): Chips That Remember and Compute (context) - Patterson - 1997
11   New DRAM Technologies: A Comprehensive Analysis of the New A.. (context) - Przybylski - 1994
11   Performance Characterization of the Alpha 21164 Microprocess.. (context) - Cvetanovic, Bhandarkar - 1996  ACM   DBLP
7   FBRAM: A New Form of Memory Optimized for 3D Graphics (context) - Deering, Schlapp et al. - 1994  DBLP
4   A 7.68 GIPS 3,84 GB/s 1W Parallel Image Processing RAM Integ.. (context) - Aimoto - 1996
2   A 1MB, 100MHz Integrated L2 Cache Memory and 128b Interface .. (context) - Giacalone - 1996
2   The Transputer (context) - Barron - 1978  ACM   DBLP



The graph only includes citing articles where the year of publication is known.


Documents on the same site (http://www.cs.berkeley.edu/~kozyraki/papers/papers.html):   More
The Architecture, Operation and Design of the Queue Management.. - Kozyrakisy (1996)   (Correct)
Pipelined Multi-Queue Management in a VLSI ATM.. - Kornaros.. (1997)   (Correct)
Evaluation of Existing Architectures in IRAM Systems - Bowman, Cardwell.. (1997)   (Correct)

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