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Abstract: In this paper, we present a statistical power estimation method where estimation time and accuracy can be balanced by assigning smaller errors to the nodes with higher power dissipation and higher errors to the nodes with lower power dissipation. To calculate the error rates for individual nodes, a quadratic programming based problem will be formulated which incorporates the distribution data of all individual node switching activities. Also, an iterative statistical power estimation system... (Update)
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BibTeX entry: (Update)
@misc{ samsung-optimizationbased,
author = "Byunggyukwak Eunseipark Samsung",
title = "An Optimization-Based Error Calculation for Statistical Power Estimation
of CMOS Logic Circuits",
url = "citeseer.ist.psu.edu/374704.html" }
Citations (may not include all citations):114 A Survey of Power Estimation Techniques in VLSI Circuits - Najm - 1994
80 A Monte Carlo approach for power estimation - Burch, Najm et al. - 1993
76 A Neutral Netlist of 10 Combinational Benchmark Circuits and.. (context) - Brglez, Fujiwara - 1985
60 Statistical estimation of the switching activity in digital .. - Xakellis, Najm - 1994
27 Estimating dynamic power consumption of CMOS circuits (context) - Cirit - 1987
9 Statistical Estimation of the Cumulative Distribution Functi.. - Ding, Wu et al. - 1997
6 Determining Accuracy Bounds for Simulation-Based Switching A.. (context) - Hill, Kang - 1996
5 Analytical Estimation of Transition Activity from Word-Level.. - Ramprasad, Shanbhag et al. - 1997
3 A Novel Methodology for Transistor-Level Power Estimation (context) - Huang, Cheng et al. - 1996
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