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by S. B. Furber, J. D. Garside, S. Temple, P. Day, N. C. Paver, Cheshire Sk Hx
ftp://ftp.cs.man.ac.uk/pub/amulet/papers/emsys96.ps.gz
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Abstract:
Abstract. AMULET1, developed in the OMI-MAP project, showed that complex asynchronous design is feasible. AMULET2e, developed in the OMI-DE project, is the next step in establishing self-timed processing as a commercially viable technology. It incorporates a new core, AMULET2, which is significantly faster than AMULET1, together with on-chip RAM which can be configured as a fixed block of RAM or as a cache. A flexible memory interface supports a 'conventional ' external memory and peripheral system, freeing the board-level designer from the asynchronous timing concerns which have made some previous self-timed chips (including AMULET1) difficult to use as components. 1.
Citations
| 53 | A micropipelined ARM – Furber, Day, et al. - 1993 |
| 44 | Four-Phase Micropipeline Latch Control Circuits – Furber, Day - 1996 |
| 34 | The Design and Implementation of an Asynchronous Microprocessor – Paver - 1994 |
| 32 | System-on-Chip Architecture – “ARM - 2000 |
| 18 | The design and evaluation of an asynchronous microprocessor – Furber, Day, et al. - 1994 |
| 16 | Some recent asynchronous system design methodologies – Gopalakrishnan, Jain - 1990 |
| 14 | The AMULET2e cache systems – Garside, Temple, et al. - 1996 |
| 10 | The MU5 Computer System – Morris, Ibbett - 1979 |
| 9 | Berkel, Handshake Circuits: An Asynchronous Architecture for VLSI Programming – van - 1993 |
| 4 | de Wiel, A SingleRail Re-implementation of a DCC Error Detector Using a Generic Standard-Cell Library – Berkel, Burgess, et al. - 1995 |
| 4 | A cache line fill circuit for a micropipelined, asynchronous microprocessor – Mehra, Garside - 1995 |
