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Abstract: This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called "dynamically variable line-size cache (D-VLS cache)". The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth. In our evaluation, it is observed that the performance improvement achieved by a directmapped D-VLS cache is about 27%, compared to a conventional direct-mapped cache... (Update)
Context of citations to this paper: More
...modes. We are currently developing techniques for the line size determination based on the second and third approaches as realistic methods[5]. In case that a direct mapped VLS cache can provide 32 byte, 64 byte, and 128 byte lines, for example, we can determine the suitable...
...multiple sequential cache blocks when the compiler detects high spatial reuse. The Dynamically Variable Line Size (D VLS) cache [11] and stride prefetching cache [9] propose similar dynamic fetch sizing techniques, but use hardware to detect the degree of spatial reuse....
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3: Run-time spatial locality detection and optimization - Johnson, Merten et al. - 1997
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BibTeX entry: (Update)
K. Inoue, K. Kai, and K. Murakami. Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. In Proceedings of the Fifth International Symposium on HighPerformance Computer Architecture, pages 218 -- 222, 1999. http://citeseer.ist.psu.edu/article/kai99dynamically.html More
@inproceedings{ inoue99dynamically,
author = "Koji Inoue and Koji Kai and Kazuaki Murakami",
title = "Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged {DRAM}/Logic {LSIs}",
booktitle = "{HPCA}",
pages = "218-222",
year = "1999",
url = "citeseer.ist.psu.edu/article/kai99dynamically.html" }
Citations (may not include all citations):64 Missing the Memory Wall: The Case for Processor/Memory Integ.. (context) - Saulsbury, Pong et al. - 1996
41 A Data Cache with Multiple Caching Strategies Tuned to Diffe.. (context) - Gonzalez, Aliagas et al. - 1995
40 Adjustable Block Size Coherent Caches - Dubnicki, LeBlanc - 1992
38 Fixed and Adaptive Sequential Prefetching in Shared Memory M.. (context) - Dahlgren, Dubois et al. - 1993
22 Designing High Bandwidth On-Chip Caches (context) - Wilson, Olukotun - 1997
21 Exploiting Spatial Locality in Data Caches using Spatial Foo.. - Kumar, Wilkerson - 1998
19 Runtime Spatial Locality Detection and Optimization - Johnson, Merten et al. - 1997
15 Parallel Processing RAM Chip with 256Mb DRAM and Quad Proces.. (context) - Murakami, Shirakawa et al. - 1997
14 Intelligent RAM (IRAM): Chips that remember and compute (context) - Patterson, Anderson et al. - 1997
6 WARTS: Wisconsin Architectural Research Tool Set (context) - Hill, Larus et al.
2 High Bandwidth, Variable Line-Size Cache Architecture for Me.. - Inoue, Koji et al. - 1998
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://kasuga.csce.kyushu-u.ac.jp/~ppram/english/ppram_paper.html):
Parallel Processing RAM (PPRAM) - Kazuaki Murakami (Correct)
Way-Predicting Set-Associative Cache for High.. - Inoue, Ishihara.. (1999) (Correct)
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