Synthesizing Communication Processors from Timing Diagram Specications
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by Werner Grass, Christine Sontheim, Stefan Lenk, Lehrstuhl F Ur Rechnerstrukturen
http://lrs.fmi.uni-passau.de/veroeff/paper/DMMS97_Budapest.ps
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Abstract:
Communication is central in any computer system in order to enable subsystems to cooperate. The diversication of o-the-shelf components and busses gives designers more freedom in designing specic optimized applications. But designers have to guarantuee
Citations
| 87 | Compiling communicating processes into delayinsensitive vlsi circuits – Martin - 1990 |
| 54 | Compiling occam into FPGAs – Page, Luk - 1991 |
| 14 | Formalized Timing Diagrams – Borriello - 1992 |
| 6 | Analysis and synthesis of concurrent digital circuits using control-flow expressions – Coelho, Micheli - 1996 |
| 3 | A Prover for VHDL-based Hardware Design – Schlor - 1995 |
| 3 | An Approach to Multi-paradigm Controller Synthesis from Timing Diagram Specifications – Tiedemann |
| 2 | Correct Compilation of Speci to Deterministic Asynchronous Circuits – Smith, Zwarico - 1995 |
| 1 | Synthesis – Grass, Tiedemann, et al. - 1997 |
| 1 | Extended timing diagrams as speci language – Lenk - 1994 |
| 1 | Timing diagrams as a speci language and their transformation into synchronous fsms – Tiedemann, Lenk, et al. - 1995 |
