Cache Write Generate For High-Performance Processing
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Abstract:
1 Abstract: Much attention has been paid to read caching and several schemes have been developed to make read caching very efficient. As a result, the performance of write caching has become a concern. This paper investigates write caching policies and how they affect the performance of memory systems. We show that write caching can greatly alter the hit/miss ratios, but only more subtly affects the performance. Many factors such as write buffers, contention, split transactions, and multilevel caches dilute the correlation of cache miss ratios to performance. A more accurate performance formula is presented taking these factors into account. This allows an incremental improvement in multiprocessor cache architectures. Cache write generate is a scheme where a cache line is validated on a write miss without fetching from memory. It avoids unnecessary reads from main memory, reduces the CPU stalling time, lowers the cache miss latency, reduces bus contention, and thus increases the available bandwidth of the memory. We compare the performance of cache write generate with the performance of write around and write allocate in single processor and shared bus multiprocessors. We use register level simulations validated by our functioning hardware prototype Proteus system. Various memory speeds and differing numbers of processors are evaluated using detailed simulation models for high performance measurement accuracy.
