HDL DRIVEN CHIP LAYOUT WITHIN THE FHDL DESIGN FRAMEWORK *
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by Craig D. Morency, Craig D. Morency, Peter M. Maurer, Peter M. Maurer, Zhicheng Wang, Zhicheng Wang
ftp://aida.csee.usf.edu/pub/faculty/maurer/tech-reports/da5_89.pdf
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Abstract:
Work is currently underway at the University of South Florida to integrate automated placement and routing with the language FHDL, for the purpose of general integrated circuit synthesis. Presented is the division of the system into two programs, which separates the tasks of layout synthesis to take advantage of CPU time and memory space. One of the over-riding principles of this work, has been to prevent any modifications of the FHDL format which would restrict the use of the language for multi-level compiled simulation. Some of the modifications which were required are presented. Most important of which is a scheme for the generation of zero/unit delay latch and flip-flop simulation models to match the I/O of actual cells.
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