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by Hamid R. Rategh, Hirad Samavati, Student Member, Student Member, Thomas H. Lee
IEEE J. Solid-State Circuits
http://www-smirc.Stanford.EDU/~hamid/papers/jssc00may-Hamid.pdf
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Abstract:
based frequency synthesizer is designed in a H PR m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of IHI dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than SR dBc. Index Terms—CMOS RF circuits, frequency synthesizers, injection-locked frequency dividers, wireless LAN. I.
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