We review behavioral and RTL test synthesis and synthesis for testability approaches that generate easily testable implementations. We also include an overview of high-level synthesis techniques to assist high-level ATPG. 1
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403
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Synthesis and Optimization of Digital Circuits
– DeMicheli
- 1994
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69
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A partial scan method for sequential circuits with feedback
– Cheng, Agarwal
- 1990
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69
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Introduction to high-level synthesis
– Gajski, Ramachandran
- 1994
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53
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Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
– Avra
- 1991
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49
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Logic Synthesis
– Devadas, Ghosh, et al.
- 1994
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41
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Hierarchical test generation using precomputed tests for modules
– Murray, Hayes
- 1990
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40
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On determining scan flip-flops in partial-scan designs
– Lee, Reddy
- 1990
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39
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Architectural level test generation for microprocessors
– Lee, Patel
- 1994
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32
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Behavioral Synthesis of Highly Testable Data Paths under Non-Scan and Partial Scan Environments
– Lee, Jha, et al.
- 1993
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31
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Built-in Logic Block Observation Technique
– Koenemann, Mucha, et al.
- 1979
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27
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A data path synthesis method for self-testable designs
– Papachristou, Chiu, et al.
- 1991
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27
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Automatic Test Knowledge Extraction From VHDL
– Vishakantaiah, Abraham, et al.
- 1992
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25
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Structural and behavioral synthesis for testability techniques
– Chen, Karnik, et al.
- 1994
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25
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An improved method for RTL synthesis with testability tradeoffs
– Harmanani, Papachristou
- 1993
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21
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Genesis: A behavioral synthesis system for hierarchical testability
– Bhatia, Jha
- 1994
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20
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CHEETA: Composition of hierarchical sequential tests using
– Vishakantaiah, Abraham, et al.
- 1993
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19
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Microarchitectural Synthesis of VLSI Designs with High Test Concurrency
– Harris, Orailoglu
- 1994
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19
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Test Synthesis in the Behavioral Domain
– Papachristou, Carletta
- 1995
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17
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Behavioral Synthesis for Easy Testability in Data Path Allocation
– Lee, Wolf, et al.
- 1992
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15
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Synthesizing for scan dependence in built-in self-testable designs
– Avra, McCluskey
- 1993
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14
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Data path allocation for synthesizing RTL designs with low BIST area overhead
– Parulkar, Gupta, et al.
- 1995
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13
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AMBIANT: Automatic Generation of Behavioral Modifications for Testability
– Vishakantaiah, Thomas, et al.
- 1993
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11
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Addressing Design for Testability at the Architectural Level
– Chickermane, Lee, et al.
- 1994
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11
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Arithmetic Built-In Self Test for High-Level Synthesis
– Mukherjee, Kassab, et al.
- 1995
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11
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Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints
– POTKONJAK, DEY, et al.
- 1995
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10
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Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs
– Dey, Potkonjak
- 1994
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9
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A Knowledge Based System for Designing Testable VLSI Chips
– Abadir, Breuer
- 1985
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9
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Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan
– Potkonjak, Dey, et al.
- 1995
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7
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Hierarchical test generation: where we are, and where we should be going
– Armstrong
- 1993
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6
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Introduction to the Scheduling Problem
– Walker, Chaudhura
- 1995
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5
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Behavioral Synthesis for Easy Testability
– Lee, WoIf, et al.
- 1992
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5
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Partial Scan at the Register-Transfer Level
– Steensma, Catthoor, et al.
- 1991
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4
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Test Synthesis: Towards Higher Levels of Abstraction
– Bennetts
- 1995
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3
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A Controller-Based Designfor -Testability Technique for Controller-datapath Circuits
– Dey, Gangaram, et al.
- 1995
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3
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Incorporating Testability Considerations
– Majumdar, Jain, et al.
- 1994
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1
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Transformations and Resynthesis for Testability of RTL Control-Data Path Specifications
– Bhattacharya, Brglez, et al.
- 1993
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1
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Non-Scan Design-for-Testability of
– Dey, Potkonjak
- 1994
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1
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Testability Analysis and Improvement from
– Gu, Kuchcinski, et al.
- 1994
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