Performance Driven Partitioning for Low Power I/O Encodings
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Abstract:
The advent of portable digital devices such as laptop personal computers has made low power CMOS circuit design an increasingly important research area. Till now, most efforts in low-power CMOS design have focused on reducing the power dissipated dynamically by reducing the number of transitions inside the CMOS circuit. In [5] Stan and Burleson showed that a significant power reduction can be achieved by using a bus encoding to reduce the number of transitions on high capacitance I/O lines at the cost of increasing the number of transitions inside the CMOS circuit on low capacitance lines. In this paper we extend the ideas presented in [5] and propose two new encoding schemes which further reduce the number of transitions on I/O lines. We then compare the three schemes in the light of the average number of transitions, additional area overhead, encoding/decoding cost, and delay.
Citations
| 280 | Algebraic Coding Theory – Berlekamp - 1968 |
| 74 | Introduction to Combinatorial Mathematics – Liu - 1968 |
| 57 | Bus-invert coding for low power I/O – Stan, Burleson - 1995 |
| 2 | Limited Weight Code for Low Power I/O – Stan, Burleson - 1994 |
