aSOC: A Scalable, Single-Chip Communications Architecture (2000) [23 citations — 3 self]
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Abstract:
Draft- submitted to PACT'00. Do not distribute. Contact authors for final version. Over the past decade the number of transistors available to VLSI chip designers has grown exponentially. While the physical capacity to integrate large systems on a single chip will soon be available, there is currently little agreement regarding the types of architectures and compilation environments that will be appropriate for these new systems. This paper examines systems-on-a-chip with an eye towards system-level adaptability and scalability. We believe that the performance-limiting bottleneck for many future systems-ona-chip will be same as the one found in many of today's board-level systems: system-wide interconnect. In this paper, a new single-chip interconnection architecture is described that not only provides scalable data transfer but also can be easily reconfigured as communication patterns change. An important aspect of the architecture is its support for compile-time, scheduled communication. To illustrate the benefits of the architecture, three DSP benchmarks have been mapped and simulated to SoC devices of assorted sizes which contain the new interconnect architecture. The described architecture is shown to be up to 5 times more efficient than bus-based SoC interconnect architectures via parallel simulation. Additionally, a preliminary layout of our interconnection architecture is shown and derived area and performance parameters are presented. 1
