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Abstract: This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system), or are not accurate enough to drive the design of the communication architecture (e.g.,... (Update)
Context of citations to this paper: More
...architecture co simulation technique, whereas the performance simulations of eArchitect are not fully functional. Lahiri et al. [7] also use traces to capture the workload of applications. For performance analysis they use an analysis technique that manipulates the...
...derive the information and statistics used in the later steps. In our work, we use the performance analysis technique presented in [25], which is comparable in accuracy to complete system simulation, while being much more efficient to employ in an iterative manner. The output...
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BibTeX entry: (Update)
K. Lahiri, A. Raghunathan, and S. Dey, "Fast performance analysis of bus-based system-on-chip communication architectures," To appear in Proc. Int. Conf. Computer-Aided Design, 1999. http://citeseer.ist.psu.edu/article/lahiri99fast.html More
@inproceedings{ lahiri99fast,
author = "Kanishka Lahiri and Anand Raghunathan and Sujit Dey",
title = "Fast performance analysis of bus-based system-on-chip communication architectures",
booktitle = "{ICCAD}",
pages = "566-573",
year = "1999",
url = "citeseer.ist.psu.edu/article/lahiri99fast.html" }
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161 Specification and Design of Embedded Systems (context) - Gajski, Vahid et al. - 1994
73 Interface Based Design (context) - Rowson, Sangiovanni-Vincentelli - 1997
45 Communication synthesis for distributed embedded systems (context) - Yen, Wolf - 1995
35 Embedded program timing analysis based on path clustering an.. - Ernst, Ye - 1997
30 Bus-based communication synthesis on system level (context) - Gasteier, Glesner - 1999
26 Integrating communication protocol selection with partitioni.. - Knudsen, Madsen - 1998
26 Performance Analysis and optimization of schedules for condi.. - Bhattacharya, Dey et al. - 1994
19 Synthesis of systemlevel communication by an allocation base.. (context) - Daveau, Ismail et al. - 1995
15 Optimizing Communication in embedded system cosimulation - Hines, Borriello - 1997
14 Static Timing Analysis of Embedded Software - Malik, Martonosi et al. - 1997
9 A Case Study on Modeling Shared Memory Access Effects During.. - Lajolo, Raghunathan et al. - 1998
8 Performance Analysis of a system of communication processes (context) - Dey, Bommu - 1997
1 On chip bus attributes specification, version v1.1.0 (context) - on-chip, DWG
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