(Enter summary)
Abstract: Recent superscalar processors highly depend on efficient
branch prediction to exploit a large amount
of instruction level parallelism. However, it is
known that branch prediction accuracy is degraded
when process switches are present. Multithreading
architectures are considered a better approach to
increase the total throughput. In multithreading
architectures, the process switch rate is very high
and even a second level cache miss causes a process
switch. In such an environment, branch... (Update)
Context of citations to this paper: More
...[KCK99b] T. Kisuki and H. Corporaal and P.M.W. Knijnenburg researched the process switches in context to branch prediction. In [KCK99a], T. Kisuki and H. Corporaal and P.M.W. Knijnenburg propose a cache to store Branch History Registers between proces switches. They use...
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BibTeX entry: (Update)
T. Kisuki, H. Corporaal, and P.M.W. Knijnenburg, Branch history register cache, Tech. report, Department of Computer Science, Leiden University, http://citeseer.ist.psu.edu/296557.html More
@misc{ kisuki-branch,
author = "T. Kisuki and H. Corporaal and P. Knijnenburg",
title = "Branch history register cache",
text = "T. Kisuki, H. Corporaal, and P.M.W. Knijnenburg, Branch history register
cache, Tech. report, Department of Computer Science, Leiden University,",
url = "citeseer.ist.psu.edu/296557.html" }
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