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by Mark A. Horowitz, Mark A. Horowitz, Chih-kong Ken Yang, Chih-kong Ken Yang, Chih-kong Ken Yang, Chih-kong Ken Yang
http://velox.stanford.edu/papers/cky_jssc_12_96.ps
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Abstract:
Abstract--- A receiver targeting OC-48 (2.488Gbps) serial data link has been designed and integrated in a 0.8��m CMOS process. An experimental receiving front end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gatespeed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3x oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of ~3x3mm 2
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