MOS C–V Characterization of Ultrathin Gate Oxide Thickness (1.3–1.8 nm)
Abstract:
Abstract — An equivalent circuit approach to MOS capacitance–voltage (g– † ) modeling of ultrathin gate oxides (1.3–1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green’s function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance. Index Terms—Device simulation, MOS g– † modeling, quantum mechanical corrections, SPICE, ultrathin gate oxide, I.
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