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  The Potential of Thread-Level Speculation based on Value Profiling

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by Anthony Dewitt, Thomas Gross
http://www.cs.cmu.edu/People/adewitt/paper/interact.ps
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Abstract:

As processors continue to provide more and more parallelism, compilers have to keep up to identify operations that can execute independently, e.g. by exploiting program properties like independent loop iterations or independent operations. Lately, various researchers have identified value locality as a potentially interesting program property: many operations produce predictable values for each execution of a program. We are interested in taking advantage of this property when compiling for a processor with thread-level parallelism. The key idea is to use predictable values to relax dependence constraints: either possible memory conflicts that rarely occur or true register dependences whose values are highly predictable. In this paper we describe our approach and present preliminary results for a partitioner that uses value profiling to group the operations of a loop body into independent threads for parallel execution. 1

Citations

664 ATOM: A system for building customized program analysis tools – Srivastava, Eustace - 1994
431 Multiscalar processors – Sohi, Breach, et al. - 1995
365 A Study of Branch Prediction Strategies – Smith - 1981
314 Value Locality and Load Value Prediction – Lipasti, Wilkerson, et al. - 1996
150 Dynamic speculation and synchronization of data dependences – Moshovos, Breach, et al. - 1997
141 Speculative versioning cache – Gopal, Vijaykumar, et al. - 1998
112 Effective Dynamic Compilation – Fast - 1996
97 Simultaneous multithreading: a platform for next-generation processors – Eggers, Emer, et al. - 1997
92 Dynamic Memory Disambiguation Using the Memory Conflict Buffer – Gallagher, Chen, et al. - 1994
58 Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation – Huang, Slavenburg, et al. - 1994
33 Architectural Support for Thread-Level Data Speculation – Steffan, Colohan, et al. - 1997
16 Architectural Implications of a Family of Irregular Applications – O’Hallaron, Shewchuk, et al. - 1998
7 Properties of a Family of Parallel Finite Element Simulations – O'HALLARON, SHEWCHUK - 1996
2 Value speculation scheduilng for highperformance processors – Fu, Jennings, et al. - 1998