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Abstract: In this paper, weinvestigate hardware implementation of block matching algorithms #BMAs# for motion estimation of moving sequences. Using systolic arrays, we propose VLSI architectures for the two-stage BMA and full search #FS# BMA. The two-stage BMA using integral projections reduces greatly computational complexity with its performance comparable to that of the FS BMA. The proposed hardware architectures for the two-stage BMA and FS BMA are faster than the conventional hardware architectures... (Update)
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BibTeX entry: (Update)
@misc{ pan-vlsi,
author = "Sung Bum Pan and Seung Soo Chae and Rae-Hong Park",
title = "VLSI Architectures for Block Matching Algorithms Using Systolic Arrays",
url = "citeseer.ist.psu.edu/280486.html" }
Citations (may not include all citations):2 Mentor Graphics Co (context) - Training - 1993
2 Mentor Graphics Co (context) - Workbook - 1993
1 Bell Syst (context) - Part - 1979
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