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Abstract: Memory-System Design Considerations for Dynamically-Scheduled Microprocessors Keith Istvan Farkas Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 1997 Dynamically-scheduled processors challenge hardware and software architects to develop designs that balance hardware complexity and compiler technology against performance targets. This dissertation presents a first thorough look at some of the issues introduced by this hardware complexity.... (Update)
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BibTeX entry: (Update)
FAR97: K. I. Farkas, P. Chow, N. P. Jouppi, Z. Vranesic, "Memory-system Design Considerations for Dynamically-Scheduled Processors", DEC/WRL Tech Report 97.1, Feb 1997. http://citeseer.ist.psu.edu/article/farkas97memorysystem.html More
@phdthesis{ farkas97memorysystem,
author = "Keith Istvan Farkas",
title = "Memory-System Design Considerations For Dynamically-Scheduled Microprocessors",
school = "University of Toronto",
month = "January",
year = "1997",
url = "citeseer.ist.psu.edu/article/farkas97memorysystem.html" }
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443 Improving Direct Mapped Cache Performance by the Addition of.. - Jouppi - 1990
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264 Combinatorial Algorithms for Integrated Circuit Layout (context) - Lengauer - 1990
249 Tolerating Latency Through Software-Controlled Data Prefetch.. - Mowry - 1994
230 Compiler Transformations for High-Performance Computing - Bacon, Graham et al. - 1993
214 Combining Branch Predictors - McFarling - 1993
201 Register allocation via coloring (context) - Chaitin, Auslander et al. - 1981
193 Superscalar Microprocessor Design (context) - Johnson - 1991
160 IMPACT: an Architectural Framework for Multiple-Instruction-.. - Chang, Mahlke et al. - 1991
156 The Multiflow Trace Scheduling Compiler - Lowney, Freudenberger et al. - 1993
155 Alpha Architecture Reference Manual (context) - Sites - 1992
149 Software Prefetching (context) - Callahan, Kennedy et al. - 1991
137 Lockup-Free Instruction Fetch/Prefetch Cache Organization (context) - Kroft - 1981
119 An Enhanced Access and Cycle Time Model for On-Chip Caches - Wilton, Jouppi - 1994
112 The Priority-Based Coloring Approach to Register Allocation (context) - Chow, Hennessy - 1990
107 Algorithmic Graph Theory (context) - Gibbons - 1985
104 Compiler-Based Prefetching for Recursive Data Structures - Luk, Mowry - 1996
98 Evaluating Stream Buffers as a Secondary Cache Replacement (context) - Palacharla, Kessler - 1994
96 AddisonWesley Publishing Company (context) - Aho, Sethi et al. - 1986
90 Reducing Memory Latency via Non-blocking and Prefetching Cac.. - Chen, Baer - 1992
89 A Practical System for Intermodule Code Optimization at Link.. - Srivastava, Wall - 1992
85 Cache Write Policies and Performance - Jouppi - 1993
81 Improvements to Graph Coloring Register Allocation - Briggs, Cooper et al. - 1994
78 Register Allocation via Graph Coloring - Briggs - 1992
75 The MIPS R10000 Superscalar Microprocessor (context) - Yeager - 1996
69 Software Pipelining - Allan, Jones et al. - 1995
56 Reducing Branch Costs via Branch Alignment - Calder, Grunwald - 1994
43 A Register Allocation Framework Based on Hierarchical Cyclic.. - Hendren, Gao et al. - 1993
41 Digital 21264 Sets New Standard (context) - Gwennap - 1996
39 Balanced Scheduling: Instruction Scheduling When Memory Late.. - Kerns, Eggers - 1993
37 Alpha AXP Architecture (context) - Sites - 1993
33 Intel's P6 Uses Decoupled Superscalar Design (context) - Gwennap - 1995
28 Register Traffic Analysis for Streamlining Inter-Operation C.. - Franklin, Sohi - 1992
26 store instruction latencies (context) - Abraham, Sugumar et al. - 1993
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22 An Investigation of the Performance of Various Dynamic Sched.. (context) - Butler, Patt - 1992
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