Standard Cells for Hardware Synthesis of LUCID Programs
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Abstract:
We describe the design of standard cell libraries in the hardware description language VHDL for Lucid operators using both demand-driven and data-driven dataflow computation. These standard cells are useful for synthesizing a VLSI system from a given design description given in Lucid. Almost all the operators for the Lucid language, and at least one operator from each of the different classes of Lucid operators for the datadriven and demand-driven model was implemented. Interfaces for hybrid models were designed and a few hybrid structures were implemented to verify the functionality and interfacing capabilities of the cells. While the use of Lucid as a hardware synthesis language seems to be promising, much additional work will be required before it becomes an effective tool and can be widely accepted.
Citations
| 75 | VHDL: Analysis and Modeling of Digital Systems – Navabi - 1993 |
| 55 | Lucid, the Dataflow Programming Language – Wadge, Ashcroft - 1985 |
| 22 | An extensional treatment of dataflow deadlock – Wadge - 1981 |
| 3 | The pLucid Programmer's Manual – Faustini, Mathews, et al. - 1984 |
| 2 | Eazyflow: A Hybrid Model for Parallel Processing – Jagannathan, Ashcroft - 1984 |
| 1 | Executing DSP applications in a fine-grained dataflow environment – Radivojevic, Herath - 1991 |
