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by H. Bederr, M. Nicolaidis, A. Guyot
ftp://verdon.imag.fr/pub/ISD/postscript/sca95b.ps.gz
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Abstract:
Several systematic design approaches are known to be representatives of the techniques well adapted for testing sequential circuits (partial and full scan, LSSD...). However in some cases, like for the test of on-line operators, ad-hoc DFT (design for testability) schemes become more suitable. Indeed, on-line arithmetic are used for high precision numbers resulting on high length operators. Thus the length of a test sequence for a scan design approach can grow quite large due to the shift in (shift out) of test values (test responses) and therefore the test application time would become prohibitive. Moreover, the arithmetic nature of these operators imply that some errors detected locally are masked before their observation at the primary outputs. In this paper we describe an analytic approach for testing on-line multipliers that allows to avoid error masking without adding extra hardware for internal state observability while maintaining a 100 % fault coverage. Compared to a DFT approach using parity trees, this method leads to a reduction of the area overhead from 7 % to 1 % and of the extra pins count from 6 to 3 in the case of the on-line multipliers considered in this paper. 1.
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