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Abstract: One of the obstacles to using RISC processors in a hard real-time environment is the unpredictability of caches. This unpredictability stems from basing them on a design that tries to optimize the average case execution time. In this paper, we propose a dual mode instruction prefetch scheme as an alternative to instruction caching schemes. In the proposed scheme, a thread is associated with each instruction block. The thread indicates the instruction block that is to be prefetched once the... (Update)
Context of citations to this paper: More
.... the execution time of a program can often be predicted more accurately on an uncached system than on a system with cache memory [27, 60, 43]. Thus, caches are often disabled for critical real time tasks to ensure the predictability required for scheduling analysis. This work...
...itself affects the very quantity it is trying to measure. 4.2. Analysis by Synthesis This technique, proposed by Minsuk Lee et al. in [3], also utilizes a timing tool to improve the predicted worst case execution time of real time tasks. In the proposed technique, a prefetch...
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0.2: Threaded Prefetching: An Adaptive Instruction Prefetch.. - Kim, Park, Park, Min.. (1993) (Correct)
0.2: Precharging Cache : A Context-Switch Robust Cache Organization - Kim (1994) (Correct)
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4: strategic memory allocation for real-time) cache design (context) - Kirk - 1989
3: MACS: A Predictable Architecture for Real-Time Systems (context) - Cogswell, Segall - 1991
2: A measurement--based performance analyser for real--time programs (context) - Kenny, Lin
BibTeX entry: (Update)
M. Lee, S. L. Min, C. Y. Park, Y. H. Bae, H. Shin, and C. S. Kim. A Dual-mode Instruction Prefetch Scheme for Improved Worst Case and Average Case Program Execution Times. In Proceedings of the 14th Real-Time Systems Symposium, (1993) 98--105. http://citeseer.ist.psu.edu/25418.html More
@inproceedings{ lee93dualmode,
author = "Minsuk Lee and Sang Lyul Min and Chang Yun Park and Young Hyun Bae and Heonshik Shin and Chong-Sang Kim",
title = "A Dual-Mode Instruction Prefetch Scheme for Improved Worst Case and Average Case Program Execution Times",
booktitle = "{IEEE} Real-Time Systems Symposium",
pages = "98-105",
year = "1993",
url = "citeseer.ist.psu.edu/25418.html" }
Citations (may not include all citations):344 Design and evaluation of a compiler algorithm for prefetchin.. - Mowry, Lam et al. - 1992
241 A study of branch prediction strategies (context) - Smith - 1981
234 Cache memories (context) - Smith - 1982
185 Branch prediction strategies and branch target buffer design (context) - Lee, Smith - 1984
149 Software prefetching (context) - Callahan, Kennedy et al. - 1991
121 Architecture for software-controlled data prefetching (context) - Klaiber, Levy - 1991
103 Experiments with a program timing tool based on sourcelevel .. (context) - Park, Shaw - 1990
93 Aspects of Cache Memory and Instruction Buffer Performance (context) - Hill - 1987
92 Reasoning about time in higher-level language software - Shaw - 1989
90 Reducing memory latency via non-blocking and prefetching cac.. - Chen, Baer - 1992
42 Strategic Memory Allocation for Real-Time) Cache Design (context) - Kirk - 1989
20 Predicting Deterministic Execution Times of Real-Time Progra.. (context) - Park - 1992
8 Predictable Cache Design for Real-Time Systems (context) - Kirk - 1990
4 Improving directed-mapped cache performance by the addition .. (context) - Jouppi - 1990
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://net.snu.ac.kr/archi/PUBLICATIONS/real-time-papers.html): More
Worst Case Timing Analysis of RISC Processors.. - Hur, Bae, Lim.. (1995) (Correct)
Analysis of Cache-related Preemption Delay in.. - Lee, Hahn, Seo.. (1996) (Correct)
Threaded Prefetching: A New Instruction Memory Hierarchy for.. - Lee, al. (1997) (Correct)
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