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Abstract: High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this problem as well, as they move towards deeper pipelines and support for multiple instruction issue. Branch prediction schemes are often used to alleviate the negative impact of branch operations by allowing the speculative execution of instructions after an unresolved branch. Another technique is to eliminate branch... (Update)
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BibTeX entry: (Update)
@article{ tyson96evaluating,
author = "Gary Tyson and Matthew Farrens",
title = "Evaluating the Effects of Predicated Execution on Branch Prediction",
journal = "International Journal of Parallel Programming",
volume = "24",
number = "2",
pages = "159--186",
year = "1996",
url = "citeseer.ist.psu.edu/249535.html" }
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