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Abstract: Caches enhance the performance of multiprocessors by reducing network traffic and average memory access latency. However, cache-based systems must address the problem of cache coherence. We propose the LimitLESS directory protocol to solve this problem. The LimitLESS scheme uses a combination of hardware and software techniques to realize the performance of a full-map directory with the memory overhead of a limited directory. This protocol is supported by Alewife, a large-scale multiprocessor.... (Update)
Context of citations to this paper: More
...the data reference status, and to invalidate or update cached copies. Snoopy buses [12, 15, 29, 35, 38] and memory directories [2, 4, 5, 14, 37] are two prominent hardware coherence mechanisms. With run time interproces2 sor dataflow information, the coherence hardware...
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BibTeX entry: (Update)
David Chaiken, John Kubiatowicz, and Anant Agarwal. LimitLESS Directories: A Scalable Cache Coherence Scheme. In Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 224--234. ACM, April 1991. http://citeseer.ist.psu.edu/article/chaiken91limitless.html More
@inproceedings{ chaiken91limitless,
author = "D. Chaiken and J. Kubiatowics and A. Agarwal",
title = "Limit{LESS} Directories: {A} Scalable Cache Coherence Scheme",
booktitle = "Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating System ({ASPLOS})",
journal = "SIGPLAN Notices",
volume = "26",
number = "4",
publisher = "ACM Press",
address = "New York, NY",
isbn = "0-89791-380-9",
pages = "224--234",
year = "1991",
url = "citeseer.ist.psu.edu/article/chaiken91limitless.html" }
Citations (may not include all citations):3 An Evaluation of Directory Schemes for Cache Coherence (context) - Horowitz - 1988 ACM DBLP
2 Memory Consistency and Event Ordering in Scalable Shared#Mem.. (context) - Gupta, Hennessy - 1990
1 Submitted for publi# cation (context) - Memo - 1990
1 Based Cache#Coherence in Large#Scale Multiprocessors (context) - Agarwal - 1990
1 Controlled Caches in the VMP Mul# tiprocessor (context) - Software - 1986
1 Kluwer Academic Publishers (context) - Structures - 1987
1 and Event Order# ing in Multiprocessors (context) - Synchronization - 1988
1 IEEE Computer# pages 74#77# June (context) - CoherentInterface - 1990
The graph only includes citing articles where the year of publication is known.
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