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by Antoon Bosselaers, Joos V
Advances in Cryptology, Proceedings Crypto'96, LNCS 1109
http://www.esat.kuleuven.ac.be/~cosicart/ps/AB-9600.ps.gz
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Abstract:
Abstract. With the advent of the Pentium processor parallelization finally became available to Intel based computer systems. One of the design principles of the MD4-family of hash functions (MD4, MD5, SHA-1, RIPEMD-160) is to be fast on the 32-bit Intel processors. This paper shows that carefully coded implementations of these hash functions are able to exploit the Pentium's superscalar architecture to its maximum effect: the performance with respect to execution on a non-parallel architecture increases by about 60%. This is an important result in view of the recent claims on the limited data bandwidth of these hash functions. Moreover, it is conjectured that these implementations are very close to optimal. It will also be shown that the performance penalty incurred by non-cached data and endianness conversion is limited, and in the order of 10 % of running time. Key words. Cryptographic hash functions, Parallel implementation,
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