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by Charles E. Leiserson, A. Gould, Keith H. Randall, Keith H. Randall
http://theory.lcs.mit.edu/~randall/papers/bachthesis.ps
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Abstract:
Circuits implemented with two-phase level-clocked latches have the theoretical potential to operate faster and require less state than equivalent circuits implemented with edge-triggered latches. We investigated to what extent one can achieve this theoretical potential with real circuits. We found that level-clocked circuits are no faster than edge-triggered circuits except when the delay between any two latches is approximately equal to the maximum gate delay. On the other hand, level-clocked circuits can often be implemented with significantly less state than equivalent edgetriggered circuits clocked at the same speed. Over one-third of the circuits tested had a reduction in state of at least 25 percent. These tests were performed in Tim, a computer-aided design tool for verification and optimization of two-phase, level-clocked circuitry. Tim consists of several efficient polynomial-time algorithms that can check circuit timing and modify circuit layout in order to meet various timing criteria. Tim was implemented in C on top of the
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