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Abstract: Common hardware exceptions, when implemented by trapping, unnecessarily serialize program execution in dynamically scheduled superscalar processors. To avoid the consequences of trapping the main program thread, multithreaded CPUs can exploit control and data independence by executing the exception handler in a separate hardware context. The main thread doesn't squash instructions after the excepting instruction, conserving fetch bandwidth and allowing execution of instructions independent of... (Update)
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BibTeX entry: (Update)
@misc{ zilles-use,
author = "Zilles",
title = "The Use of Multithreading . . .",
url = "citeseer.ist.psu.edu/242201.html" }
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27 The Cascaded Predictor: Economical and Adaptive Branch Targe.. - Driesen, Holzle - 1998
26 Alpha Microprocessor Hardware Reference Manual (context) - Corporation - 1998
25 The Direct Cost of Virtual Function Calls in C (context) - Driesen, Holzle - 1996
18 The Effects of Mispredicted-Path Execution on Branch Predict.. (context) - Jourdan, Hsing et al. - 1997
16 A Study of Control Independence in Superscalar Processors - Rotenberg, Jacobsen et al. - 1999
9 Concurrent Event Handling Through Multithreading (context) - Keckler, Dally et al. - 1999
4 A Commercial Multi-Threaded RISC Processor (context) - Storino, Aipperspach et al. - 1998
3 Department of EE-Systems (context) - Song, Dubois et al. - 1998
2 Alpha EV7: A Scalable Single-chip SMP (context) - Bannon - 1998
1 Adding Fast Interrupts to Superscalar Processors (context) - Henry - 1994
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