Abstract:
Novel techniques are needed to cope with the increasing complexity of digital systems and the increasing densities offered by sub-micron fabrication techniques. Designers rely on high-level modeling to manage the complexity of these systems. Although VHDL can be used for modeling at the system level, it lacks certain feature that make the task of system level modeling with VHDL more difficult than it should be. Software programmers have used object-oriented programming techniques to handle complexity of large software systems. VHDL lacks features to support such object oriented techniques. This thesis details the design, implementation, and analysis of SAVANT and University of Adelaide VHDL Extensions (SUAVE). SUAVE extends VHDL with features for object-orientation, genericity, encapsulation, abstract communication, and dynamic creation of processes. The SUAVE analyzer is built as an extension to SCRAM, the VHDL analyzer built as part of the Standard Analyzer of VHDL Applications for Next-generation Technologies (SAVANT) project. The SUAVE analyzer uses an intermediate representation that is an extension of the AIRE standard. SUAVE extensions are designed to make it a complete superset
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