In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown here how properties relevant for scheduling and verification of specification models like boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets may be represented in the FunState model. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in form of a periodic graph. 1
|
1713
|
Statecharts: A visual formalism for complex systems
– Harel
- 1987
|
|
1128
|
Symbolic Model Checking
– McMillan
- 1993
|
|
437
|
On the Formal Semantics of Statecharts
– Harel, Pnueli, et al.
- 1987
|
|
286
|
Synchronous data flow
– Lee, Messerschmitt
- 1987
|
|
271
|
Static scheduling of synchronous data flow programs for digital signal processing
– Lee, Messerschmitt
- 1987
|
|
207
|
Hardware-Software Cosynthesis for Microcontrollers
– Ernst, Henkel, et al.
- 1993
|
|
164
|
Dataflow process networks
– Lee, Parks
- 1995
|
|
136
|
Hardware-Software Co-Design of Embedded Systems: The POLIS Approach
– Balarin, Chiodo, et al.
- 1997
|
|
131
|
A framework for comparing models of computation
– Lee, Sangiovanni-Vincentelli
- 1998
|
|
121
|
Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model
– Buck
- 1993
|
|
117
|
Coloured Petri Nets: A high-level Language for System Design
– Jensen
- 1990
|
|
97
|
A comparison of statecharts variants
– Beeck
- 1984
|
|
92
|
Marked directed graphs
– Commoner, Holt, et al.
- 1971
|
|
65
|
et al. Hardware-Software Co-Design of Embedded Systems: The Polis Approach
– Balarin, Chiodo, et al.
- 1997
|
|
54
|
Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits
– Ku, Micheli
- 1992
|
|
29
|
Scheduling of conditional process graphs for the synthesis of embedded systems
– Eles, Kuchcinski, et al.
- 1998
|
|
23
|
Telecommunications Systems Engineering Using SDL
– Saracco, Smith, et al.
- 1989
|
|
21
|
Speccharts: A vhdl front-end for embedded systems
– Vahid, Narayan, et al.
- 1995
|
|
21
|
Detecting cycles in dynamic graphs in polynomial time
– Kosaraju, Sullivan
- 1988
|
|
20
|
The Olympus synthesis system
– Micheli, Ku, et al.
- 1990
|
|
20
|
Software synthesis for real-time information processing systems
– Thoen, Corncro, et al.
- 1995
|
|
19
|
Combining multiple models of computation for scheduling and allocation
– Ziegenbein, Ernst, et al.
- 1998
|
|
19
|
Symbolic model checking of process networks using interval diagram techniques
– Strehl, Thiele
- 1998
|
|
17
|
Argonaute: graphical description, semantics and verification of reactive systems by using a process algebra
– Maraninchi
- 1989
|
|
16
|
Effective heterogeneous design and cosimulation
– Chang, Kalavade, et al.
- 1995
|
|
16
|
Cyclo-Static Data Flow: Model and implementation
– Engels, Bilsen, et al.
- 1994
|
|
16
|
Compile-time scheduling of dynamic constructs in dataflow program graphs
– Ha, Lee
- 1997
|
|
15
|
Representation of process mode correlation for scheduling
– Ziegenbein, Richter, et al.
- 1998
|
|
15
|
Quasi-Static Scheduling of Embedded Software Using Free-Choice Petri Nets
– Sgroi, Lavagno, et al.
- 1998
|
|
15
|
Scheduling hardware/software systems using symbolic techniques
– Strehl, Thiele, et al.
- 1999
|
|
13
|
PCC: A Modeling Technique for Mixed Control/Data Flow Systems
– Grotker, Schoenen, et al.
- 1997
|
|
12
|
Dynamic data flow and control flow in high level dsp code synthesis
– Pankert, Mauss, et al.
- 1994
|
|
10
|
Representation of function variants for embedded system optimization and synthesis
– Richter, Ziegenbein, et al.
- 1999
|
|
6
|
A preliminary study of hierarchical finite state machines with multiple concurrency models
– Girault, Lee, et al.
- 1997
|
|
5
|
Analysis of free schedule in periodic graphs
– Backes, Schwiegelshohn, et al.
- 1992
|
|
5
|
Development of a static load balancing tool
– Bilsen, Wauters, et al.
- 1993
|
|
4
|
Regular state machines
– Thiele, Teich, et al.
- 2000
|
|
4
|
Recurrences, iteration, and conditionals in statically scheduled block diagram languages
– Lee
- 1988
|
|
4
|
Scheduling hardware /software systems using symbolic techniques
– Strehl, Thiele, et al.
- 1999
|
|
3
|
Some problems in dynamic and periodic graphs
– Orlin
- 1984
|
|
2
|
FunState---functions driven by state machines
– Thiele, J, et al.
- 1998
|
|
1
|
High-level embedded system specifications based on process activation conditions. Accepted for publication
– Boung, Huss, et al.
- 1999
|
