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Abstract: Decoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred is a self-timed decoupled, pipelined computer architecture based on micropipelines. We present the architecture of Fred, with specific details on a micropipelined implementation that includes support ... (Update)
Context of citations to this paper: More
...design, such as the decoupled branch mechanism and exception model. Early versions of the Fred architecture have been discussed elsewhere [9,10,11]. A prototype of Fred has been implemented as a detailed VHDL model to investigate the performance 2 and behavior of the Fred...
...such as the decoupled branch mechanism and exception model. Early versions of the Fred architecture have been discussed elsewhere [33,34]. Detailed descriptions of the most recent implementation are contained in the following chapters. 1 Fred is not an acronym, and it...
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BibTeX entry: (Update)
W. F. Richardson, E. L. Brunvand, FRED : An Architecture for a Self-Timed Decoupled Computer », Computer Science Department, University of Utah, 1997. http://citeseer.ist.psu.edu/article/richardson95fred.html More
@techreport{ richardson95fred,
author = "William F. Richardson and Erik Brunvand",
title = "Fred: An Architecture for a Self-Timed Decoupled Computer",
number = "UUCS-95-008",
month = "8,",
year = "1995",
url = "citeseer.ist.psu.edu/article/richardson95fred.html" }
Citations (may not include all citations):230 Limits of instruction-level parallelism - Wall - 1990
83 Communications of the ACM (context) - Sutherland - 1989
80 The design of an asynchronous microprocessor (context) - Martin, Burns et al. - 1989
67 Measuring the parallelism available for very long instructio.. (context) - Nicolau, Fisher - 1984
65 PIPE: A VLSI decoupled architecture (context) - Goodman, Hsieh et al. - 1985
43 A micropipelined ARM - Furber, Day et al. - 1993
37 Counterflow pipeline processor architecture - Sproull, Sutherland - 1994
28 The Design and Implementation of an Asynchronous Microproces.. (context) - Paver - 1994
28 Reduced Instruction Set Computer Architectures for VLSI (context) - Katevenis - 1985
17 Computer Architecture News (context) - Wulf, computer - 1988
17 The NSR processor (context) - Brunvand - 1993
9 Interrupt handling for out-of-order execution processors (context) - Torng, Day - 1993
8 A comparison of superscalar and decoupled access /execute ar.. - Farrens, Ng et al. - 1993
7 Measurement and evaluation of the MIPS architecture and proc.. (context) - Gross, Hennessy et al. - 1988
7 software tradeoffs for increased performance (context) - Hennessy, Jouppi et al. - 1982
5 Using FPGAs to prototype a self-timed computer (context) - Brunvand - 1992
5 The NSR processor prototype - Richardson, Brunvand - 1992
4 Precise exception handling for a self-timed processor - Richardson, Brunvand - 1995
4 Macromodular system design (context) - Clark, Molnar - 1973
4 The architecture and system method for DDM1: A recursively s.. (context) - Davis - 1978
Documents on the same site (http://www.cs.utah.edu/~willrich/async/mypapers.html): More
Fred: An Architecture for a Self-Timed Decoupled Computer - Richardson, Brunvand (1996) (Correct)
Precise Exception Handling for a Self-Timed Processor - Richardson, Brunvand (1995) (Correct)
Architectural Considerations for a Self-Timed Decoupled.. - Richardson, Brunvand (Correct)
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