See this document in CiteSeerX!

Processor Mechanisms for Software Shared Memory  (Make Corrections)  
Nicholas Parks Carter
Lecture Notes in Computer Science



  Home/Search   Context   Related

Links:   ACM   DBLP

 
View or download:
stanford.edu/pub/p...er_phd_thesis.ps.Z
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  stanford.edu/cva_publications (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: This thesis describes and evaluates the effectiveness of four hardware mechanisms for software shared memory: block status bits, a global translation lookaside buffer, a fast, non-blocking, event system, and dedicated thread slots for software handlers. These mechanisms have been integrated into the M-Machine's MAP processor, and accelerate tasks which are common to many shared-memory protocols, including detection of remote memory references, invocation of software handlers, and determination... (Update)

Active bibliography (related documents):   More   All
0.6:   Mechanisms for Efficient, Protected Messaging - Lee   (Correct)
0.5:   Fast Thread Communication and Synchronization Mechanisms for a.. - Keckler (1998)   (Correct)
0.5:   Architectural Support for Single Address Space Operating.. - Koldinger, Chase, Eggers (1992)   (Correct)

Similar documents based on text:   More   All
0.4:   The MMachine Multicomputer - Fillo, Keckler, Dally, al. (1995)   (Correct)
0.2:   Appears in the Proceedings of the 6th International Conference on.. - And   (Correct)
0.1:   Stream Register Files with Indexed Access - Nuwan Jayasena Mattan (2004)   (Correct)

BibTeX entry:   (Update)

@article{ carter00processor,
    author = "Nicholas P. Carter and William J. Dally and Whay S. Lee and Stephen W. Keckler and Andrew Chang",
    title = "Processor Mechanisms for Software Shared Memory",
    journal = "Lecture Notes in Computer Science",
    volume = "1940",
    pages = "120--??",
    year = "2000",
    url = "citeseer.ist.psu.edu/221036.html" }
Citations (may not include all citations):
443   Improving Direct-Mapped Cache Performance by the Addition of.. - Jouppi - 1990  ACM   DBLP
362   The stanford FLASH multiprocessor (context) - Kuskin - 1994  ACM   DBLP
357   The Directory-Based Cache Coherence Protocol for the DASH Mu.. (context) - Lenoski, Laudon et al. - 1990  ACM   DBLP
268   Tempest and Typhoon: user-level shared memory - Reinhardt, Larus et al. - 1994
222   The SGI Origin: a ccNUMA highly scalable server (context) - Laudon, Lenoski - 1997
212   The MIT Alewife machine: architecture and performance - Agarwal - 1995  DBLP
170   The national technology roadmap for semiconductors (context) - Association - 1997
170   LimitLESS directories: a scalable cache coherence scheme - Chaiken, Kubiatowicz et al. - 1991  ACM   DBLP
157   IVY: a shared virtual memory system for parallel computing (context) - Li - 1988  DBLP
156   The Multiflow trace scheduling compiler - Lowney, Freudenberger et al. - 1993  ACM
122   Firefly: a multiprocessor workstation (context) - Thacker, Stewart et al. - 1987  ACM   DBLP
107   The DASH prototype: implementation and performance (context) - Lenoski, Laudon et al. - 1992  DBLP
87   software coherent shared memory on a clustered remote-write .. (context) - Stets, Dwarkadas et al. - 1997
80   Machine multicomputer: an architectural evaluation (context) - Noakes, Wallach et al. - 1993
63   Capability-based addressing (context) - Fabry - 1974  ACM   DBLP
56   Machine multicomputer (context) - Fillo, Keckler et al. - 1995
53   Processor Coupling: integrating compile time and runtime sch.. - Keckler, Dally - 1992  DBLP
52   Decoupled hardware support for distributed shared memory (context) - Reinhardt, Pfile et al. - 1996  ACM   DBLP
51   MGS: a multigrain shared memory system - Yeung, Kubiatowicz et al.  DBLP
44   Teapot: language support for writing memory coherence protoc.. (context) - Chandra, Richards et al. - 1996  DBLP
43   Integrated predicated and speculative execution in the IMPAC.. - August - 1998  ACM   DBLP
41   Integration of message passing and shared memory in the Stan.. - Heinlein, Gharachorloo et al. - 1994  ACM   DBLP
40   Sparcle: an evolutionary processor design for large-scale mu.. - Agarwal - 1993
26   Using prediction to accelerate coherence protocols - Mukherjee, Hill - 1998  ACM   DBLP
23   Hardware support for fast capability-based addressing - Carter, Keckler et al. - 1994  ACM   DBLP
16   Exploiting fine-grain thread-level parallelism on the MIT Mu.. - Keckler, Dally et al. - 1998
4   software-only approach for supporting fine-grained shared me.. (context) - Scales, Gharachorloo et al. - 1996
4   Application performance on the Alewife multiprocessor (context) - Bianchini - 1994
4   Department of Electrical Engineering and Computer Science (context) - Gurevich, operating et al. - 1995  ACM
3   The effects of explicitly parallel mechanisms on the Multi-A.. - Chang, Dally et al. - 1998  ACM
2   Commercial multiprocessing systems (context) - Satyanarayanan - 1980
2   protected message interface in the MIT M-Machine (context) - Lee, Dally et al. - 1998
2   Fast thread communication and synchronization mechanisms for.. - Keckler - 1998  ACM
2   SPUR memory system architecture (context) - Wood, Eggers et al. - 1987
1   VLSI datapath choices: cell-based vs (context) - Chang - 1998
1   Department of Electrical Engineering and Computer Science (context) - Shultz, the et al. - 1997  ACM
1   Software register synchronization for super-scalar processor.. (context) - Maskit - 1997  ACM

Documents on the same site (http://cva.stanford.edu/cva_publications.html):   More
An Assembler and Linker System for the M-Machine Software Project - Gurevich (1994)   (Correct)
Fast Thread Communication and Synchronization Mechanisms for a.. - Keckler (1998)   (Correct)
Efficient, Protected Message Interface in the MIT.. - Lee, Dally, Keckler..   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC