Low-Power Design of Page-Based Intelligent Memory
by Justin Hensley, Aneet Chopra, Mark Oskin, Timothy Sherwood, Aamir Farooqui, Frederic T. Chong
ftp://theory.cs.ucdavis.edu/swc98/abstracts/hensley-chopra-oskin-sherwood-farooqui-chong.ps
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Abstract:
Citations
| 258 | Garp: A MIPS Processor with a Reconfigurable Coprocessor. FCCM’97 pagg 12-21 – Hauser, Wawrzynek - 1997 |
| 81 | Reconfigurable Architectures for General-Purpose Computing – DeHon - 1996 |
| 75 | Active Pages: A Computation Model for Intelligent Memory – Oskin, Chong, et al. |
| 32 | System-on-Chip Architecture – “ARM - 2000 |
| 25 | The Triptych FPGA Architecture – Borriello, Ebeling, et al. - 1995 |
| 18 | An FPGA for implementing asynchronous circuits – Hauck, Burns, et al. - 1994 |
| 12 | The Ultimate RISC – Jones - 1988 |
| 10 | MONTAGE: An FPGA for Synchronous and Asynchronous Circuits – Hauck, Borriello, et al. - 1992 |
| 4 | Strongarm sa110: A 160mhz 32b 0.5w cmos arm processor – Santhanam - 1996 |
| 3 | Pga-stc: Programmable gate array for implementing self-timed circuits – Maheswaran, Akella - 1998 |
