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  Experimental validation of parallel computation models on the Intel Paragon (1998) [10 citations — 5 self]

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by Ben H. H. Juurlink
Paderborn University
http://cardit.et.tudelft.nl/~benj/pubs/ipps.98.ps.gz
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Abstract:

Experimental data validating some of the proposed parallel computation models on the Intel Paragon is presented. This architecture is characterized by a large bandwidth and a relatively large startup cost of a message transmission, which makes it extremely important to employ bulk transfers. The models considered are the BSP model, in which it is assumed that all messages have a fixed short size, and the BPRAM, in which block transfers are rewarded. 1.

Citations

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42 The input/output complexity of transitive closure – Ullman, Yannakakis - 1991
39 SUNMOS for the Intel Paragon: A brief user’s guide – Maccabe, McCurley, et al. - 1994
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20 The NX message passing interface – Pierce - 1994
15 Practical Parallel List Ranking – Sibeyn, Guillaume, et al. - 1999
12 The E-BSP model: Incorporating unbalanced communication and general locality into the BSP model – Juurlink, Wijshoff - 1996
7 Experimental validation of models of parallel computation – Snyder - 1995
3 Technology advances in the Intel Paragon system – Brandenburg - 1993