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  Minimum-cost bounded-skew clock routing (1995) [20 citations — 4 self]

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by Jason Cong, Cheng-kok Koh
IEEE Intl. Symp. Circuits and Systems
http://ballade.cs.ucla.edu:8080/~kohck/papers/bst/bsttr.ps.Z
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Abstract:

In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm constructs a bounded-skew tree (BST) in two steps: (i) a bottom-up phase to construct a binary tree of shortest-distance feasible regions which represent the loci of possible placements of clock entry points, and (ii) a top-down phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of routing solutions with skew and wirelength trade-off. 1

Citations

63 Zero skew clock routing with minimum wirelength – CHAO, HSU, et al. - 1992
61 Exact zero skew – Tsay - 1991
34 A clustering-based optimization algorithm in zero-skew routings – EDAHIRO - 1993
30 Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay – van - 1990
29 A symmetric clock-distribution tree and optimized highspeed interconnections for reduced clock-skew – BAKOGLU, WALKER, et al. - 1986
25 Matching-based methods for high-performance clock routing – Cong, Kahng, et al. - 1993
20 Perfect-balance planar clock routing with minimal path-length – Zhu, Dai - 1992
19 Pillage “Skew and Delay Optimization for Reliable Buffered Clock Trees – Pullela, Menezes, et al. - 1993
17 Minimum Path-Length Equi-Distant Routing – Edahiro - 1992
12 Skew sensitivity minimization of buffered clock tree – Chung, Cheng - 1994
12 Planar-DME: Improved planar zero-skew clock routing with minimum pathlength delay – Kahng, Tsao - 1994
12 Low-cost single-layer clock trees with exact zero Elmore delay skew – Kahng, Tsao - 1994
12 Process-Variation-Tolerant Clock Skew Minimization – Lin, Wong - 1994
11 A buffer distribution algorithm for high-speed clock routing – Cho, Sarrafzadeh - 1993
5 A specified delay accomplishing clock router using multiple layers – Seki, Inoue, et al. - 1994
4 A symmetric clock-distributiontree and optimized high-speed interconnections for reduced clock skew – Bakoglu, Walker, et al. - 1986
3 Clock routing for high performanceICs – Jackson, Srinivasan, et al. - 1990
2 Clock routingfor high performance ICs – Jackson, Srinivasan, et al. - 1990
2 Process-variation-tolerantclock skew minimization – Lin, Wong - 1994
1 Kahng and C.-W. A Tsao, "On the Bounded-Skew Routing Tree Problem – Huang, B - 1995
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