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Abstract: . We present a formal model of asynchronous communication between two digital hardware devices. The model takes the form of a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into that consumed by an independently clocked processor, given the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on communications at ISO protocol level 1 (physical level).... (Update)
Context of citations to this paper: More
...0. Physically, due to some disturbance, it takes some amount of time to the signal on the bus to change from high to low or vice versa [23, 24]. So the value of r is chosen arbitrarily among 0 and 1 if the digitised value is neither 0 nor 1. Therefore r is unreliable when the...
.... To our knowledge, there has been some work on the veri cation of instances of the protocol either using theorem proving techniques [Moo93] or model checking [IG99,Vaa] and one work presenting full parameter analysis using PVS and the Duration Calculus, however, without...
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BibTeX entry: (Update)
J Strother Moore, "A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol", NASA CR-4433, June 1992. http://citeseer.ist.psu.edu/article/moore93formal.html More
@article{ moore94formal,
author = "J Strother Moore",
title = "A Formal Model of Asynchronous Communication and its Use in Mechanically Verifying a Biphase Mark Protocol",
journal = "Formal Aspects of Computing",
volume = "6",
number = "1",
pages = "60--91",
year = "1994",
url = "citeseer.ist.psu.edu/article/moore93formal.html" }
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