Static Power Optimization of Deep Submicron CMOS Circuits for Dual
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by V T Technology
http://www.ece.arizona.edu/~qi/papers/iccad98.ps
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Abstract:
In this paper we address the problem of leakage power minization under delay constraints of CMOS digital circuit for dual V T technology. A novel and efficient heuristic alogrithm based on the circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to one order of magnitude power reduction can be achieved without any delay increases.
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