An Optimization Technique For Dual-Output Domino Logic
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by Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
http://uivlsi.csl.uiuc.edu/~ramprasa/islped99.ps.gz
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Abstract:
We present an optimization technique, termed clockgenerating (CG) domino, for dual-output domino logic that reduces area, clock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24 % respectively over dual-output domino and a 48 % power reduction for the largest circuit. 1
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