Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators (1993) [79 citations — 10 self]
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@INPROCEEDINGS{Babb93virtualwires:,author = {Jonathan William Babb and Jonathan William Babb},
title = {Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators},
booktitle = {IEEE Workshop on FPGAs for Custom Computing Machines},
year = {1993},
pages = {142--151}
}
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Abstract:
Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneously and are only switched at emulation clocking speeds. Virtual Wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency of the FPGA. A virtual wire connects a logical output of one FPGA to a logical input on another FPGA. Virtual Wires relax the absolute limits imposed on gate utilization. The resulting increase in bandwidth reduces the need for
