Analysis of Queueing Displacement Using Switch Port Speedup
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Abstract:
Current high-speed packet switching systems, ATM in particular, have large port buffering requirements because of their support of bursty data applications, their use of reactive flow control over ever increasing link speeds and the separation of QoS classes as well as connection groups to dedicated buffers. The use of highly integrated ASIC technology for implementing high-degree and high-speed switch fabrics is facing a technology mismatch in the sense that today's chip technology does not allow to integrate on-chip the highspeed switching fabric with the huge amount of memory required to buffer all switch ports. Consequently, many designs are based on the principles of queueing displacement, i.e., they attempt to move the queueing point off-chip. This is usually done by considerably speedingup the on-chip switch output ports and placing a second external stage of buffering between the switch fabric and the outgoing link circuitry. Such designs are very popular and are used by many current ATM switch vendors. While such schemes are widely used, no rigorous analysis has so far been offered to evaluate the design trade-offs and to quantify the design points.
