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Abstract: This paper presents a new approach to automate the generation of interface logic required to interface two components, possibly with incompatible communication protocols. Our tool is specifically targeted to handle synchronous and asynchronous protocols with diverse timing constraints such as propagation, setup and hold times and multiple operation modes such as read, write and burst mode. Since the components and the generated interface logic are specified in VHDL, we expect our tool to... (Update)
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BibTeX entry: (Update)
@misc{ collins-interface,
author = "Jeff Collins",
title = "Interface Logic Generation for VHDL-Specified Components",
url = "citeseer.ist.psu.edu/165528.html" }
Citations (may not include all citations):161 Specification and Design of Embedded Systems (context) - Gajski, Vahid et al. - 1994
33 Synthesis and optimization of interface transducer logic (context) - Borriello, Katz - 1987
25 Interfacing incompatible protocols using interface process g.. (context) - andD, Gajski - 1995
20 software co-synthesis system (context) - Chou, Ortega et al. - 1995
19 Design of system interface modules (context) - Sun, Broderson - 1992
1 Direct implementation of asynchronous control units (context) - Holaar - 1982
1 Savant: Standard analyzer of vhdl applications for next-gene.. (context) - Cincinatti, Inc
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