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by Russell J. Petersen, Brad L. Hutchings, D. Jeffs, Wynn C. Stirling
http://splish.ee.byu.edu/docs/fpga-dsp-ths.ps.gz
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Abstract:
Digital signal processing (DSP) is an application area requiring intense amounts of I/O and computation, often being applied in areas that require a realtime response. The real-time nature of many DSP systems combined with their intensive computation and data flow requires performance beyond that which can be achieved with a conventional microprocessor. As a result, many custom hardware systems have been designed and developed to provide the required performance. These custom systems, however, have the disadvantage of inflexibility and a high cost of development. The DSP processor attempts to overcome the inflexibility and development costs of custom hardware by providing flexibility through software instruction decoding and execution and high performance through custom arithmetic and I/O components. Reconfigurable hardware using FPGAs has also generated interest for use in implementing digital signal processing systems due to its ability to implement custom hardware solutions while still maintaining flexibility through system reprogramming. Using reconfigurable hardware it is hoped that a significant performance improvement can be achieved over the DSP processor without sacrificing system flexibility. This thesis quantifies the ability of reconfigurable hardware using FPGAs to provide a performance improvement over the DSP processor in the area of digital signal processing. A study of multiplier implementation methods and their performance when implemented on FPGAs has been performed for three separate FPGAs. Three common DSP algorithms have also been chosen and implemented on the three FPGAs with their performance being compared to that of equivalent implementations using DSP processor and custom hardware systems.
Citations
|
171
|
Computer Arithmetic Algorithms
– Koren
- 1993
|
|
87
|
Computer Arithmetic: Principles, Architecture and Design
– Hwang
- 1979
|
|
85
|
The Programmable Logic Data
– Xilinx
- 1994
|
|
59
|
Constructing hardware/software systems from a single description
– Page
- 1996
|
|
44
|
Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines
– Shirazi, Walters, et al.
- 1995
|
|
43
|
Real-time image processing on a custom computing platform
– Athanas, Abbott
- 1995
|
|
35
|
Teramac—Configurable Custom Computing
– Amerson, Carter, et al.
- 1995
|
|
34
|
The Splash 2 Software Environment
– Arnold
- 1993
|
|
32
|
A Reconfigurable Multiprocessor IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths
– Chen, Rabaey
- 1992
|
|
29
|
Two’s complement pipeline multipliers
– Lyon
- 1976
|
|
13
|
Comparing the performance of fpga-based custom computers with general-purpose computers for dsp applications
– Bergmann, Mudge
- 1994
|
|
12
|
FPGA implementation of digital filters
– Chou, Mohanakrishnan, et al.
- 1993
|
|
10
|
Configurable Logic Array (CLAy) Data Sheet
– Semiconductor
- 1993
|
|
9
|
Multiplier policies for digital signal processing
– Ma, Taylor
- 1990
|
|
9
|
An FPGA-based hardware accelerator for image processing
– Ross, Vellacott, et al.
- 1993
|
|
6
|
A Programmable Image Processing System using FPGAs
– Chan, Ngai, et al.
- 1993
|
|
6
|
Fast integer multipliers fit in FPGAs (EDN
– Chapman
- 1993
|
|
6
|
An efficient FIR filter architecture
– Evans
- 1993
|
|
6
|
Accelerate FPGA Macros with One-Hot Approach
– Knapp
- 1990
|
|
4
|
Parallelism in fast Fourier transform hardware
– Gold, Bially
- 1973
|
|
3
|
FIR filter fits in an FPGA using a bit-serial approach
– Andraka
- 1993
|
|
3
|
FPGA-Based DSP Systems
– Wahab, Puckey
- 1993
|
|
2
|
Application-Specific Architectures for Field-Programmable VLSI Technologies
– Gebotys, Gebotys
- 1994
|
|
2
|
On a bit-serial input and bit-serial output multiplier
– Gnanasekaran
- 1983
|
|
2
|
Multimedia powerhouse
– Guttag
- 1994
|
|
2
|
A pipelined, high-precision FFT architecture
– Hopkinson, Butler
- 1992
|
|
1
|
Study and implementation of a real time 3x3 programmable convolver with reconfigurable technology
– Barros, Akil
- 1992
|
|
1
|
VLSI architectures for DSP applications: Current trends
– Bayoumi
- 1992
|
|
1
|
Improved DSP ICs eye new horizons
– Bursky
- 1993
|
|
1
|
FPGA implementation of the LRU algorithm for video compression
– Fatemi, Idris, et al.
- 1994
|
|
1
|
Reconfigurable hardware for digital signal processing algorithms
– Hood
- 1993
|
|
1
|
Programmable DSP architectures, part 1
– Lee
- 1988
|
|
1
|
Programmable DSP architectures, part 2
– Lee
- 1989
|
|
1
|
Mediastation 5000: An integrated multimedia video and audio processing system
– Lee, Gove, et al.
- 1994
|
