Alex Ramírez, Josep-L. Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero  Home/Search
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Abstract: In this paper we address the important problem of instruction fetch for future wide issue superscalar processors. Our approach focuses on understanding the interaction between software and hardware techniques targeting an increase in the instruction fetch bandwidth. That is the objective, for instance, of the Hardware Trace Cache (HTC). We design a profile based code reordering technique which targets a maximization of the sequentiality of instructions, while still trying to minimize... (Update)
Context of citations to this paper: More
...operating system code. A detailed description of the code layout optimizations available in Spike can be found in previous papers [5, 20, 22]. The Spike optimizer algorithm consists of three parts. The basic blocks of a procedure are reordered to sequentialize the most...
...1. 2Run time code straightening by dynamic optimizers translators A problem with the static code straightening techniques [28,34,36] is that they require profilebased optimization, and, in reality, not many programs are compiled this way. Actual run time behavior of...
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BibTeX entry: (Update)
Alex Ram'irez, Josep Ll. Larriba-Pey, Carlos Navarro, Josep Torrellas, and Mateo Valero. Software trace cache. Proceedings of the 13th Intl. Conference on Supercomputing, page to appear, June 1999. http://citeseer.ist.psu.edu/article/ramirez99software.html More
@inproceedings{ ramirez99software,
author = "Alex Ramirez and Josep-Lluis Larriba-Pey and Carlos Navarro and Josep Torrellas and Mateo Valero",
title = "Software trace cache",
booktitle = "International Conference on Supercomputing",
pages = "119-126",
year = "1999",
url = "citeseer.ist.psu.edu/article/ramirez99software.html" }
Citations (may not include all citations):407 Trace scheduling: A technique for global microcode compactio.. (context) - Fisher - 1981 DBLP
107 Achieving high instruction cache performance with an optimiz.. (context) - Hwu, Chang - 1989 ACM DBLP
93 Optimization of instruction fetch mechanism for high issue r.. - Conte, Menezes et al. - 1995
75 Increasing the instruction fetch rate via multiple branch pr.. - Yeh, Marr et al. - 1993 ACM DBLP
53 Procedure placement using temporal ordering information - Gloy, Blackwell et al. - 1997
51 Optimizing instruction cache performance for operating syste.. - Torrellas, Xia et al. - 1995 ACM DBLP
47 Efficient procedure mapping using cache line coloring - Hashemi, Kaeli et al. - 1997 ACM DBLP
28 The effect of code expanding optimizations on instruction ca.. - Chen, Chung et al. - 1993 ACM DBLP
22 Improving trace cache effectiveness with branch promotion an.. - Patel, Evers et al. - 1998 ACM DBLP
10 Alternative fetch and issue techniques from the trace cache .. (context) - Friendly, Patel et al. - 1997
6 Trace cache: a low latency aprroach to high bandwith instruc.. (context) - Rottenberg, Benett et al. - 1996
6 on Programming Languaje Design and Implementation (context) - Pettis, Hansen et al. - 1990
4 Temporal-based procedure reordering for improved instruction.. (context) - Kalamaitianos, Kaeli - 1998 ACM DBLP
4 Code reordering of decision support systems for optimized in.. (context) - Ram'irez, Larriba-Pey et al. - 1998
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