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Abstract: We describe techniques that use symmetry to perform efficient invariant checking. We start by developing the theory needed to exploit symmetry for designs specified at the gate level. This is followed by a proof of the inadequacy of BDD based methods for highly symmetric designs; this motivates the use of explicit state enumeration. Exact symmetry reduction has been conjectured to be computationally intractable; we propose fast heuristic reduction procedures. Experiments with these routines... (Update)
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0.9: Heuristic Symmetry Reduction for Invariant Verification - William Hung Adnan (Correct)
0.2: Formal Methods in VLSI System Design - Aziz (1996) (Correct)
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BibTeX entry: (Update)
@misc{ hung-heuristic,
author = "William Hung",
title = "Heuristic Symmetry Reduction for Invariant Verification",
url = "citeseer.ist.psu.edu/145283.html" }
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