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Abstract: In static CMOS technology the decomposition of the nodes of a circuit netlist can significantly reduce the overall power dissipation of the circuit. We present a normalization algorithm which extracts the largest recognizable nodes of the given structure. Then we examine a known decomposition algorithm for the normalized nodes and propose a new one which is provable optimal and tractable for moderate node size. Resulting reduction of the overall switching activity on standard benchmark circuits ... (Update)
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BibTeX entry: (Update)
@misc{ th-node,
author = "Winfried Nöth and Reiner Kolla",
title = "Node Normalization and Decomposition in Low Power Technology Mapping",
url = "citeseer.ist.psu.edu/140154.html" }
Citations (may not include all citations):158 Estimation of Average Switching Activity in Combinational an.. - Ghosh, Devadas et al. - 1992
98 Transition Density: A New Measure of Activity in Digital Cir.. - Najm - 1993
27 Estimating Dynamic Power Consumption of CMOS Circuits (context) - Cirit - 1987
13 Decomposition of Logic Functions for Minimum Transition Acti.. (context) - Murgai, Brayton et al. - 1994
7 The Fanout Structure of Switching Functions (context) - Hayes - 1975
5 Technology Decomposition and Mapping Targeting Low Power Dis.. (context) - Tsui, Pedram et al. - 1993
2 Reducing Power Dissipation in CMOS Circuits by Signal Probab.. (context) - Hossain, Zheng et al. - 1996
2 TROY: A Tree-Based Approach to Logic Synthesis and Technolog.. (context) - Noth, Hinsberger et al. - 1996
1 Power Efficient Technology Decomposition and Mapping Under a.. (context) - Tsui, Pedram et al. - 1994
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