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by Gitanjali M. Swamy, Vigyan Singhal, Robert K. Brayton
in Proc. Intl. Conf. on Computer Design
http://www-cad.eecs.berkeley.edu/~gms/pub/gmsIrchIwls.ps.Z
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Abstract:
Computing the set of reachable states of a finite state machine, is an important component of many problems in the synthesis, and formal verification of digital systems. Computing the reachable states is computationally expensive due to the "explosion " in the number of states in real designs. However, the process of design is usually iterative, and the designer may modify and recompute information many times. Unfortunately, the reachability computation is called each time the designer modifies the system, because current methods for reachability analysis are not incremental. The representation of the reachable states that is currently used [1] in synthesis and verification, is inherently non-updatable; in addition it tends to have a large representation, even when the finite state machine itself has a compact representation. We solve all these problems by presenting alternate ways to represent the reachable set, and incremental algorithms that can update the new representation each time the designer changes the system. The incremental algorithms use the reachable set computed at a previous iteration, and information about the changes to the system to update it, rather than compute the reachable set from the beginning. This results in considerable savings in time, as demonstrated by the results 1
Citations
|
2315
|
Graph-based algorithms for boolean function manipulation
– Bryant
- 1986
|
|
1128
|
Symbolic Model Checking
– McMillan
- 1992
|
|
373
|
Symbolic model checking: 10 states and beyond
– Burch, Clarke, et al.
- 1992
|
|
127
|
Sequential Circuit Design Using Synthesis and Optimization
– Sentovich, Singh, et al.
- 1992
|
|
118
|
Implicit state enumeration of finite state machines using BDD's
– Touati, Savoj, et al.
|
|
94
|
A unified framework for the formal verification of sequential circuits
– Coudert, Madre
- 1990
|
|
63
|
Representing circuits more efficiently in symbolic model checking
– Burch, Clarke, et al.
|
|
24
|
Minimization of symbolic relations
– Lin, Somenzi
- 1990
|
|
18
|
On the computational complexity of incremental algorithms
– Ramalingam, Reps
- 1991
|
|
10
|
Redundancy identification and removal based on implicit state enumeration
– Cho, Hachtel, et al.
- 1991
|
|
10
|
Efficient Formal Design Verification: Data Structure + Algorithms
– Ranjan, Aziz, et al.
- 1994
|
|
6
|
Heuristic Algorithms for Early Quantification and Partial Product Minimization
– Hojati, Krishnan, et al.
- 1993
|
|
5
|
Checking Language Containment using BDDs
– Touati, Brayton, et al.
- 1990
|
|
5
|
Temporal and Modal Logic," in Formal Models and Semantics
– Emerson
- 1990
|
|
4
|
Incremental formal design verification
– Swamy, Brayton
- 1994
|
|
3
|
et al., "HSIS: A BDD-Based Environment for Formal Verification
– Brayton
- 1994
|
|
1
|
Temporal and Modal Logic,"in Formal Models and Semantics
– Emerson
- 1990
|
|
1
|
et al., "HSIS: ABDD-BasedEnvironment for Formal Verification
– Brayton
- 1994
|
