Download:
|
by Thomas S. Brasier, Philip H. Sweany, Steven J. Beaty
In Proc. Intl. Conf. Parallel Architectures and Compilation Techniques (PACT’95) (Limassol
http://emess.mscd.edu/~beaty/Dossier/Papers/Craig.ps
Add To MetaCart
Abstract:
In compilers for machines with instruction-level parallelism, the phases of register assignment and instruction scheduling can be antagonistic. Whichever phase is executed first can have negative effects on the other's performance. This paper describes a framework, called CRAIG (Combining Register Assignment Interference Graphs), that combines register assignment and instruction schedulingto alleviate the phase-orderingproblem. CRAIG utilizes information gained from instruction scheduling before register assignment as an upper bound on the freedom needed by the instruction scheduler to attain its "best " schedule. CRAIG then allows heuristics to choose how close to the "best " schedule one can get before the cost of additional register pressure is too high. Within the context of this framework, the paper evaluates an instance of CRAIG called CRAIG 0. 1
Citations
|
7715
|
Computers and Intractability: A Guide to the Theory of NP-Completeness
– Garey, Johnson
- 1979
|
|
342
|
Register allocation and spilling via graph coloring
– Chaitin
- 1982
|
|
168
|
Register Allocation via coloring
– Chaitin, Auslander, et al.
- 1981
|
|
125
|
The ParaScope Parallel Programming Environment
– Cooper, Hall, et al.
- 1993
|
|
104
|
Integrating Register Allocation and Instruction Scheduling for RISCs
– Bradlee, Eggers, et al.
- 1991
|
|
102
|
Code Scheduling and Register Allocation in Large Basic Blocks
– Goodman, Hsu
- 1988
|
|
76
|
Dynamic dependency analysis of ordinary programs
– Austin, Sohi
- 1992
|
|
62
|
Single instruction stream parallelism is greater than two
– Butler, Yeh, et al.
- 1991
|
|
61
|
Register allocation with instruction scheduling: a new approach
– Pinter
- 1993
|
|
40
|
Local microcode compaction techniques
– Landskov, Davidson, et al.
- 1980
|
|
29
|
Phase Ordering of Register Allocation and Instruction Scheduling
– Freudenberger, Ruttenberg
- 1992
|
|
24
|
Time and parallel processor bounds for FORTRAN-like loops
– Banerjee, Shen, et al.
- 1979
|
|
23
|
A scheduler-sensitive global register allocator
– Norris, Pollock
- 1993
|
|
20
|
Overview of the Rocket retargetable C compiler
– Sweany, Beaty
- 1994
|
|
6
|
A Machine-Independent Approach to the Production of Optimal Horizontal Microcode
– DeWitt
- 1976
|
|
3
|
An analysis of instruction-level parallelism in several common benchmarks
– Peterman
- 1993
|
|
1
|
A scheduler-sensitiveglobal register allocator
– NORRIS, ANDPOLLOCK
- 1993
|
|
1
|
A Machine-IndependentApproachto the Production of Optimal Horizontal Microcode
– DEWITT
- 1976
|
|
1
|
OverviewoftheROCKET retargetable C compiler
– SWEANY, BEATY
- 1994
|
