Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun  Home/Search
Context Related
| stanford.edu/publication...ISCA97.ps.gz stanford.edu/publication...dramws.ps.gz berkeley.edu/isca97worksho...w2106.ps Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: stanford.edu/publications (more) From: stanford.edu/pu...lications.shtml (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: We evaluate the performance of a single chip multiprocessor integrated with DRAM. We compare the performance of this architecture with that of a more conventional chip which only has on-chip SRAM. The DRAM-based architecture with four processors performs an average of 52% faster than the SRAM-based architecture on floating point applications with large working sets. This is performance difference is significantly better than a uniprocessor DRAM-based architecture, which only performs an average ... (Update)
Context of citations to this paper: More
.... proposed vector processor or quad processors integrated with DRAM are proposed in order to exploit the wide on chip DRAM bandwidth [2] [4]. In this paper we evaluate the performance of a powerful microprocessor architecture, such as a multiprocessor, when the integrated DRAM...
...in large trac to the slow o chip DRAM then it becomes tempting to put much denser DRAM on chip so that much of the trac are kept on chip. In [35] simulations arm intuition. 45 5.5.2 C RAM C RAM [9] is a simple proposal to put SIMD processor into DRAM IC. Even the author admit...
Cited by: More
An Equal Area Comparison of Embedded DRAM and SRAM.. - Keltcher, Richardson.. (2000) (Correct)
On-chip MRAM as a High-Bandwidth, Low-Latency.. - Desikan, Lefurgy.. (2002) (Correct)
Exploiting Application Parallelism Using Advanced Intelligent.. - Huang (1999) (Correct)
Similar documents (at the sentence level):
62.6%: A Single Chip Multiprocessor Integrated with High Density.. - Yamauchi, Hammond, Olukotun (1997) (Correct)
11.9%: The Hierarchical Multi-Bank DRAM: A High-Performance.. - Yamauchi, Hammond.. (1997) (Correct)
Active bibliography (related documents): More All
0.2: Considerations In The Design Of Hydra: A.. - Hammond, Olukotun (1998) (Correct)
0.1: A Quantitative Analysis of Reconfigurable Coprocessors for.. - Miyamori (1998) (Correct)
0.1: Exploiting Coarse-Grain Parallelism in the MPEG-2 Algorithm - Iwata, Olukotun (1998) (Correct)
Similar documents based on text: More All
0.4: Yield Enhancement Considerations for a Single-Chip.. - Rudack, Niggemeyer (1999) (Correct)
0.2: Command Vector Memory Systems: High Performance at Low Cost - Corbal, Espasa, Valero (1998) (Correct)
0.2: IRAM Design for Multimedia Applications - Bum-Sik Kim Yun (1997) (Correct)
Related documents from co-citation: More All
4: Missing the Memory Wall: The Case for Processor/Memory Integration (context) - Saulsbury, Pong et al. - 1996
4: The case for a SingleChip Multiprocessor (context) - Olukotun, Nayfeh et al. - 1996
3: The SimOS approach (context) - Rosenblum, Herrod et al. - 1995
BibTeX entry: (Update)
T. Yamauchi, L. Hammond, and K. Olukotun, "A SingleChip Multiprocessor Integrated with DRAM," Stanford University Technical Report No. CSL-TR-97-731, August 1997. http://citeseer.ist.psu.edu/article/yamauchi97single.html More
@techreport{ yamauchi97single,
author = "Tadaaki Yamauchi and Lance Hammond and Olukotun and Kunle",
title = "A Single Chip Multiprocessor Integrated with High Density {DRAM}",
number = "CSL-TR-97-731",
pages = "34",
year = "1997",
url = "citeseer.ist.psu.edu/article/yamauchi97single.html" }
Citations (may not include all citations):97 The Case for a Single-Chip Multiprocessor (context) - Olukotun, Chang et al. - 1996 ACM DBLP
75 The MIPS R10000 Superscalar Microprocessor (context) - Yeager - 1996 ACM
64 Missing the Memory Wall: The Case for Processor/Memory Integ.. (context) - Saulsbury, Pong et al. - 1996 DBLP
38 Evaluation of Design Alternatives for a Multiprocessor Micro.. (context) - Nayfeh, Hammond et al. - 1996 ACM DBLP
37 The Energy Efficiency of IRAM Architectures - Fromm, Perissakis et al. - 1997 ACM DBLP
14 Intelligent RAM (IRAM): Chips that Remember and Compute (context) - Patterson, Anderson et al. - 1997
12 The SUIF Compiler System: A Parallelizing and Optimizing Res.. (context) - Wilson, French et al. - 1994 ACM
9 The SimOS approach (context) - Rosenblum, Herrod et al. - 1995
3 The Hierachical Multi-Bank DRAM: A High-Performance Architec.. (context) - Yamauchi, Hammond et al. - 1997
3 Fully Self-timing Data-Bus Architecture for 64-Mb DRAMs (context) - Yamauchi - 1995
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://katrina.stanford.edu/publications.html): More
A Single Chip Multiprocessor Integrated with High Density.. - Yamauchi, Hammond, Olukotun (1997) (Correct)
The Hierarchical Multi-Bank DRAM: A High-Performance.. - Yamauchi, Hammond.. (1997) (Correct)
A Single-Chip Multiprocessor - Hammond, al. (1997) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC