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Abstract: Behavioral-level synthesis techniques have traditionally focussed on design of a fully-hardwired application-specific implementation of a given computation. In this paper, new techniques are presented for the synthesis of reconfigurable hardware. The technique is applicable for synthesis of several classes of designs, including: 1) design for fault tolerance against permanent faults, 2) design for improved manufacturability, and 3) design of Application Specific Programmable Processors (ASPPs)... (Update)
Context of citations to this paper: More
.... proposed algorithms were validated on the set of DSP, video, control, and communication examples shown in Table III and described in [25]. Supporting tools from the Hyper behaviorallevel synthesis system [14] were used for other synthesis tasks. The table shows all relevant...
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Synthesis of Application-Specific Highly-Efficient.. - Low-Power.. (2003) (Correct)
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1998) (Correct)
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BibTeX entry: (Update)
L. Guerra, M. Potkonjak, and J. Rabaey, "Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's," UCLA Comput. Sci. Dep., Tech. Rep. 960005, 1996. http://citeseer.ist.psu.edu/article/guerra93behaviorallevel.html More
@misc{ guerra96behaviorallevel,
author = "L. Guerra and M. Potkonjak and J. Rabaey",
title = "Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's",
text = "L. Guerra, M. Potkonjak, and J. Rabaey, Behavioral-level synthesis of heterogeneous
BISR reconfigurable ASIC's, UCLA Comput. Sci. Dep., Tech. Rep. 960005, 1996.",
year = "1996",
url = "citeseer.ist.psu.edu/article/guerra93behaviorallevel.html" }
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