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by Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John Hennessy
http://www.csl.cornell.edu/~heinrich/papers/FLASH.ps
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Abstract:
The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both the hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine's global memory, a port to the interconnection network, an I/O interface, and a custom node controller called MAGIC. The MAGIC chip handles all communication both within the node and among nodes, using hardwired data paths for efficient data movement and a programmable processor optimized for executing protocol operations. The use of the protocol processor makes FLASH very flexible--- it can support a variety of different communication mechanisms--- and simplifies the design and implementation. This paper presents the overall architecture of FLASH and MAGIC, and discusses the base cachecoherence and message-passing protocols. Latency and occupancy numbers, which are derived from our system-level simulator and our Verilog code, are given for several of the common protocol operations. The paper also describes our software strategy, implementation strategy, and current status. The two architectural techniques for communicating data among processors in a scalable multiprocessor are
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